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| bq4024/bq4024Y 128Kx16 Nonvolatile SRAM Features (R) Data retention in the absence of power (R) Automatic write-protection during power-up/power-down cycles (R) Industry-standard 40-pin 128K x 16 pinout (R) Conventional SRAM operation; unlimited write cycles (R) 10-year minimum data retention in absence of power (R) Battery internally isolated until power is applied General Description The CMOS bq4024 is a nonvolatile 2,097,152-bit static RAM organized as 131,072 words by 16 bits. The integral control circuitry and lithium energy source provide reliable nonvolatility coupled with the unlimited write cycles of standard SRAM. The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC falls out of tolerance, the SRAM is unconditionally writeprotected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The bq4024 uses extremely low standby current CMOS SRAMs, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM. The bq4024 requires no external circuitry and is compatible with the industry-standard 2Mb SRAM pinout. Pin Connections NC CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 VSS DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC WE A16 A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 Pin Names A0-A16 Address inputs DQ0-DQ15 Data input/output CE OE WE NC VCC VSS Chip enable input Output enable input Write enable input No connect +5 volt supply input Ground Block Diagram 40-Pin DIP Module PN402401.eps Selection Guide Part Number bq4024MA -85 bq4024MA -120 Maximum Access Time (ns) 85 120 Negative Supply Tolerance -5% -5% Part Number bq4024YMA -85 bq4024YMA -120 Maximum Access Time (ns) 85 120 Negative Supply Tolerance -10% -10% Sept. 1992 1 bq4024/bq4024Y Functional Description When power is valid, the bq4024 operates as a standard CMOS SRAM. During power-down and power-up cycles, the bq4024 acts as a nonvolatile memory, automatically protecting and preserving the memory contents. Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD. The bq4024 monitors for VPFD = 4.62V typical for use in systems with 5% supply tolerance. The bq4024Y monitors for VPFD = 4.37V typical for use in systems with 10% supply tolerance. When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become high impedance, and all inputs are treated as "don't care." If a valid access is in process at the time of power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time tWPT, write-protection takes place. As VCC falls past VPFD and approaches 3V, the control circuitry switches to the internal lithium backup supply, which provides data retention until valid VCC is applied. When VCC returns to a level above the internal backup cell voltage, the supply is switched back to VCC. After VCC ramps above the VPFD threshold, write-protection continues for a time tCER (120ms maximum) to allow for processor stabilization. Normal memory operation may resume after this time. The internal coin cells used by the bq4024 have an extremely long shelf life and provide data retention for more than 10 years in the absence of system power. As shipped from Benchmarq, the integral lithium cells are electrically isolated from the memory. (Selfdischarge in this condition is approximately 0.5% per year.) Following the first application of VCC, this isolation is broken, and the lithium backup provides data retention on subsequent power-downs. Truth Table Mode Not selected Output disable Read Write CE H L L L WE X H H L OE X H L X I/O Operation High Z High Z DOUT DIN Power Standby Active Active Active Absolute Maximum Ratings Symbol VCC VT TOPR TSTG TBIAS TSOLDER Note: Parameter DC voltage applied on VCC relative to VSS DC voltage applied on any pin excluding VCC relative to VSS Operating temperature Storage temperature Temperature under bias Soldering temperature Value -0.3 to 7.0 -0.3 to 7.0 0 to +70 -40 to +70 -10 to +70 +260 Unit V V C C C C For 10 seconds VT VCC + 0.3 Conditions Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. Sept. 1992 2 bq4024/bq4024Y Recommended DC Operating Conditions (TA = 0 to 70C) Symbol VCC VSS VIL VIH Note: Parameter Supply voltage Supply voltage Input low voltage Input high voltage Minimum 4.5 4.75 0 -0.3 2.2 Typical 5.0 5.0 0 Maximum 5.5 5.5 0 0.8 VCC + 0.3 Unit V V V V V Notes bq4024Y bq4024 Typical values indicate operation at TA = 25C. (TA = 0 to 70C, VCCmin VCC VCCmax) Typical 5 2.5 Maximum 2 1 0.4 11 5 Unit A A V V mA mA Conditions/Notes VIN = VSS to VCC CE = VIH or OE = VIH or WE = VIL IOH = -1.0 mA IOL = 2.1 mA CE = VIH CE VCC - 0.2V, 0V VIN 0.2V, or VIN VCC - 0.2V Min. cycle, duty = 100%, CE = VIL, II/O = 0mA bq4024 bq4024Y DC Electrical Characteristics Symbol ILI ILO VOH VOL ISB1 ISB2 Parameter Input leakage current Output leakage current Output high voltage Output low voltage Standby supply current Standby supply current Minimum 2.4 - ICC VPFD VSO Note: Operating supply current 4.55 95 4.62 4.37 3 200 4.75 4.50 - mA V V V Power-fail-detect voltage Supply switch-over voltage 4.30 - Typical values indicate operation at TA = 25C, VCC = 5V. Capacitance (TA = 25C, F = 1MHz, VCC = 5.0V) Symbol CI/O CIN Note: Parameter Input/output capacitance Input capacitance Minimum Typical Maximum 10 20 Unit pF pF Conditions Output voltage = 0V Input voltage = 0V This parameter is sampled and not 100% tested. Sept. 1992 3 bq4024/bq4024Y AC Test Conditions Parameter Input pulse levels Input rise and fall times Input and output timing reference levels Output load (including scope and jig) Test Conditions 0V to 3.0V 5 ns 1.5 V (unless otherwise specified) See Figures 1 and 2 Figure 1. Output Load A Figure 2. Output Load B Read Cycle Symbol tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH (TA = 0 to 70C, VCCmin VCC VCCmax) -85 Parameter Min. 85 5 0 0 0 10 Max. 85 85 45 35 25 -120 Min. 120 5 0 0 0 10 Max. 120 120 60 45 35 Unit ns ns ns ns ns ns ns ns ns Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A Conditions Read cycle time Address access time Chip enable access time Output enable to output valid Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output in high Z Output hold from address change Sept. 1992 4 bq4024/bq4024Y Read Cycle No. 1 (Address Access) 1,2 Read Cycle No. 2 (CE Access) 1,3,4 Read Cycle No. 3 (OE Access) 1,5 Notes: 1. WE is held high for a read cycle. 2. Device is continuously selected: CE = OE = VIL. 3. Address is valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Device is continuously selected: CE = VIL. Sept. 1992 5 bq4024/bq4024Y Write Cycle Symbol tWC tCW tAW tAS tWP tWR1 tWR2 tDW tDH1 tDH2 tWZ tOW Notes: (TA = 0 to 70C, VCCmin VCC VCCmax) -85 Parameter Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high-Z Output active from end of write Min. 85 75 75 0 65 5 15 35 0 10 0 0 Max. 30 -120 Min. 120 100 100 0 85 5 15 45 0 10 0 0 Max. 40 Units ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) Measured from address valid to beginning of write. (2) Measured from beginning of write to end of write. (1) Measured from WE going high to end of write cycle. (3) Measured from CE going high to end of write cycle. (3) Measured to first low-to-high transition of either CE or WE. Measured from WE going high to end of write cycle.(4)] Measured from CE going high to end of write cycle. (4) I/O pins are in output state. (5) I/O pins are in output state. (5) Conditions/Notes 1. A write ends at the earlier transition of CE going high and WE going high. 2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low. 3. Either tWR1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state. Sept. 1992 6 bq4024/bq4024Y Write Cycle No. 1 (WE-Controlled) 1,2,3 Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5 Notes: 1. CE or WE must be high during address transition. 2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If OE is high, the I/O pins remain in a state of high impedance. 4. Either tWR1 or tWR2 must be met. 5. Either tDH1 or tDH2 must be met. Sept. 1992 7 bq4024/bq4024Y Power-Down/Power-Up Cycle (TA = 0 to 70C) Symbol tPF tFS tPU Parameter VCC slew, 4.75 to 4.25 V VCC slew, 4.25 to VSO VCC slew, VSO to VPFD (max.) Minimum 300 10 0 Typical Maximum Unit s s s Time during which SRAM is write-protected after VCC passes VPFD on power-up. TA =25C. (2) Delay after VCC slews down past VPFD before SRAM is writeprotected. Conditions tCER Chip enable recovery time 40 80 120 ms tDR Data-retention time in absence of VCC 10 - - years tWPT Write-protect time 40 100 150 s Notes: 1. Typical values indicate operation at TA = 25C, VCC = 5V. 2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the accumulated time in absence of power beginning when power is first applied to the device. Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Power-Down/Power-Up Timing Sept. 1992 8 bq4024/bq4024Y MA: 40-Pin A-Type Module 40-Pin MA (A-Type Module) Dimension Minimum A 0.365 A1 0.015 B 0.017 C 0.008 D 2.070 E 0.710 e 0.590 G 0.090 L 0.120 S 0.075 All dimensions are in inches. Maximum 0.375 0.023 0.013 2.100 0.740 0.630 0.110 0.150 0.110 Sept. 1992 9 bq4024/bq4024Y Ordering Information bq4024 MA Temperature: blank = Commercial (0 to +70C) Speed Options: 85 = 85 ns 120 = 120 ns Package Option: MA = A-type module Supply Tolerance: no mark = 5% negative supply tolerance Y = 10% negative supply tolerance Device: bq4024 128K x 16 NVSRAM Sept. 1992 10 Notes 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated |
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